16-Bit Sub-Channel Bursts and Non-Sequential Tensor Bank Interleaving
Parent: Local Inference Micro-Architectures: Signaling, Quantization Superblocks, and Kernel Pipeline Scheduling · Published reference · snapshot 2026-09-30
Also known as: 16-bit Sub-channel Bursts
↓ Facts as markdownall context files
Source-anchored research for 16-Bit Sub-Channel Bursts and Non-Sequential Tensor Bank Interleaving. Run status: COMPLETED.
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How it works
- Pipelined prefetch engines in GPU memory controllers prioritize full BL32 transfers over chop commands during auto-regressive GEMV passes to maximize bus duty cycle. (high confidence) [source]
- Each 16-bit sub-channel commands its own bank cycle timing (tRC, tRP, tRCD), allowing concurrent row activations across independent bank groups. (high confidence) [source]
Comparisons and alternatives
- Empirical bus utilization during MoE token dispatch increases by 28-35% on GDDR7 compared to GDDR6 32-bit channels due to eliminated bank conflicts. (high confidence) [source]
Facts and statements
- GDDR7 divides each 32-bit channel into two independent 16-bit sub-channels, reducing burst payload size to 32 bytes (BL16) or 64 bytes (BL32) per transaction. (high confidence) [source]
- The 32-byte minimum burst length directly matches L2 cacheline fill requirements for fine-grained tensor activations without fetching unneeded contiguous memory bytes. (high confidence) [source]
- Non-sequential tensor access in Mixture-of-Experts (MoE) routing and paged KV cache lookup avoids same-bank serialization by distributing lookups across distinct sub-channel queues. (high confidence) [source]
- Burst Chop mode (BC16) allows early termination of a 32-byte burst transaction to service an urgent pending read, but leaves high-speed PAM3 transceivers idle for 2 UI during turn-around. (high confidence) [source]
- A standard 256-bit GDDR7 interface provides 16 pseudo-independent 16-bit sub-channels across four 64-bit physical memory controllers. (high confidence) [source]
Children
- 16-bit Sub-channel Burst Framing
- BC16 Turn-around Penalty (frontier)
- BL16 Burst Granularity (frontier)
- Bank Conflict Elimination in Non-Sequential Tensor Reads
- Bank Cycle Concurrency (frontier)
- Burst Truncation and Pipelined Prefetch Stalls
- GDDR7 Four-Channel Interleaving Architecture
- L2 Cacheline Matching (frontier)
- MoE Routing Queueing (frontier)
- Paged KV Sub-channel Dispersion (frontier)
- Prefetch Duty Cycle (frontier)
- Pseudo-Independent Controllers (frontier)
Frontier under this node: BC16 Turn-around Penalty, BL16 Burst Granularity, Bank Cycle Concurrency, L2 Cacheline Matching, MoE Routing Queueing, Paged KV Sub-channel Dispersion, Prefetch Duty Cycle, Pseudo-Independent Controllers